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sm5841h nippon precision circuits? nippon precision circuits inc. audio multi-function digital filter overview the sm5841h is an 8-times oversampling (interpo- lation) digital ?ter for digital audio reproduction equipment. it accepts 16 or 18-bit input data, and outputs data in 16, 18 or 20-bit format, making a wide range of interfaces possible. it also features digital deemphasis for 3 sampling frequencies, a noise shaper to reduce quantization noise, a dc off- set output and other circuits. features functions n 2-channel processing n 8-times (8fs) oversampling (interpolation) n digital deemphasis (fs = 48/44.1/32 khz) n serial input data 2s complement, msb ?st, 16/18-bit n serial output data 2s complement, msb ?st, 16/18/20-bit n 1st-order noise shaper (for 16/18-bit output only) n 256fs/384fs system clock selectable n output data dc offset (approximately 0.8%) on/off control n ttl-compatible input/outputs n 5 v (standard) supply n 3.2 v operating voltage n molybdenum-gate cmos filter characteristics n 3-stage dc fir interpolation ?ter 1st stage (fs ? 2fs), 69-tap 2nd stage (2fs ? 4fs), 13-tap 3rd stage (4fs ? 8fs), 9-tap n iir deemphasis ?ter for gain and phase character- istics close to those of analog ?ters n over?w limiter built-in applications n digital ampli?rs n cd players n dat players n dbs systems n pcm systems ordering infomation device package sm5841hp 18pin dip SM5841HS 22pin sop
sm5841h nippon precision circuits? pinout 18-pin dip 22-pin sop package dimensions 18-pin dip (unit: mm) 22-pin sop (unit: mm) dsf2 cko vss cki cksl wsl1 wsl2 lrci dsf1 dol ofst 1 2 3 4 5 6 7 8 10 sm5841hp rst bcko vdd 17 18 15 16 13 14 11 9 12 dor wcko bcki din wsl2 cko vss cki cksl wsl1 (nc) vdd (nc) bcki lrci ofst bcko wcko 1 2 3 4 5 6 7 8 10 SM5841HS dsf1 dsf2 dol din 21 22 19 20 17 18 15 16 13 14 11 9 12 rst dor (nc) (nc) 1.27max 2.54typ 1.20 + 0.30 - 0 22.05 + 0.20 - 0.30 0.45 + 0.14 - 0.05 6.20 0.25 5.00max 0.51min 3.00min 7.62typ 0.25 0.05 015 1.27 7.8 0.3 5.4 0.2 13.9 0.3 0.05 0.05 1.8 0.1 0.4 0.1 0.5 0.2 0.15 - 0.05 + 0.1 0 to 10?
sm5841h nippon precision circuits? block diagram pin description sop dip name i/o 1 description 1 1 wsl1 ip input/output data select pins 8 6 wsl2 ip 2 2 cki ip system clock input 3 3 cksl ip system clock select input. 384fs when high, and 256fs when low. 4 4 cko o system clock output. the cki is rst buff ered before output on cko. 5 5 vss ground 6 nc no connection 7 nc no connection 9 7 dsf1 ip deemphasis select inputs 10 8 dsf2 ip 11 9 rst ip system reset. reset and initialization when rst is low. 12 10 bcko o output bit clock input data interface system clock bcko dol cksl cki cko dsf1 wsl1 rst wcko dor timing controller dsf2 vdd vss lrci bcki din ofst filter and attenuation airthmetic block interface output date deemphasis controler wsl2 input/output word length selector wsl1 wsl2 noise shaper input bit length output bit length high high off 18 bits 20 bits high low on 18 bits 18 bits low high on 16 bits 18 bits low low on 16 bits 16 bits dsf1 dsf2 deemphasis sampling frequency low low on 44.1 khz low high on 48.0 khz high low off high high on 32.0 khz
sm5841h nippon precision circuits? specifications absolute maximum ratings v ss = 0 v recommended operating conditions v ss = 0 v 13 11 dor o right-channel 8fs data output 14 12 dol o left-channel 8fs data output 15 13 wcko o output w ord clock 16 14 vdd 5 v supply 17 nc no connection 18 nc no connection 19 15 ofst ip output data dc offset select input. summing on when high, and off when low. 20 16 lrci ip input data sample rate (fs) clock 21 17 bcki ip input bit clock 22 18 din ip input data 1. ip = input with pull-up resistor parameter symbol rating unit supply v oltage r ange v dd - 0.3 to 7.0 v input voltage r ange v in - 0.3 to v dd + 0.3 v storage temper ature r ange t stg - 40 to 125 c power dissipation p d 250 mw soldering temperature t sld 255 c soldering time t sld 10 s parameter symbol rating unit supply v oltage r ange v dd 3.2 to 5.5 v oper ating temperature r ange t opr - 20 to 80 c sop dip name i/o 1 description
sm5841h nippon precision circuits? dc electrical characteristics standard voltage: v dd = 4.5 to 5.5 v, v ss = 0 v, t a = - 20 to 80 c low voltage: v dd = 3.2 to 4.5 v, v ss = 0 v, t a = - 20 to 80 c parameter symbol condition rating unit min typ max current consumption i dd v dd = 5.0 v 1 1. f sys = 384fs = 20 mhz, no output load 40ma high-level input voltage 2 2. pins cksl , ofst v ih1 0.7v dd v low-level input voltage 2 v il1 0.3v dd v cki a c-coupled input voltage v inac sine wave input 0.3v dd v p-p high-level input voltage 3 3. pins lrci, din, bcki, dsf1, dsf2, wsl1, wsl2, rst v ih2 2.4 v low-level input voltage 3 v il2 0.5 v high-level output voltage 4 4. pins cko, dol, dor, bcko, wcko v oh i oh = - 0.4 ma 2.5 v low-level output voltage 4 v ol i ol = 1.6 ma 0.4 v cki high-level input current i ih1 v in = v dd ?020a cki low-level input current i il1 v in = 0 v 10 20 a low-level input current 3 i il2 v in = 0 v 10 20 a input leakage current 2, 3 i lh v in = v dd 1.0 a input leakage current 2 i ll v in = 0 v 1.0 a parameter symbol condition rating unit min typ max current consumption i dd v dd = 3.4 v 1 1. f sys = 384fs = 18.5 mhz, no output load 20ma high-level input voltage 2 2. pins cksl , ofst v ih1 0.7v dd v low-level input voltage 2 v il1 0.3v dd v cki a c-coupled input voltage v inac sine wave input 0.3v dd v p-p high-level input voltage 3 3. pins lrci, din, bcki, dsf1, dsf2, wsl1, wsl2, rst v ih2 2.4 v low-level input voltage 3 v il2 0.5 v high-level output voltage 4 4. pins cko, dol, dor, bcko, wcko v oh i oh = - 0.2 ma 2.5 v low-level output voltage 4 v ol i ol = 0.8 ma 0.4 v cki high-level input current i ih1 v in = v dd 12a cki low-level input current i il1 v in = 0 v 12 a low-level input current 3 i il2 v in = 0 v 12 a input leakage current 2, 3 i lh v in = v dd 1.0 a input leakage current 2 i ll v in = 0 v 1.0 a
sm5841h nippon precision circuits? ac electrical characteristics clock (cki) standard voltage: v dd = 4.5 to 5.5 v, v ss = 0 v, t a = - 20 to 80 c low voltage: v dd = 3.2 to 4.5 v, v ss = 0 v, t a = - 20 to 80 c parameter symbol condition rating unit cksl system clock min typ max high-level clock pulse width t cwh high 384fs 23 250 ns low 256fs 35 500 low-level clock pulse width t cwl high 384fs 23 250 ns low 256fs 35 500 clock pulse cycle t ci high 384fs 50 500 ns low 256fs 76 1000 parameter symbol condition rating unit cksl system clock min typ max high-level clock pulse width t cwh high 384fs 25 250 ns low 256fs 50 500 low-level clock pulse width t cwl high 384fs 25 250 ns low 256fs 50 500 clock pulse cycle t ci high 384fs 54 500 ns low 256fs 108 1000 t ci t cwh cki 0.5 v dd t cwl over 0.7 v dd under 0.3 v dd
sm5841h nippon precision circuits? serial input timing ( bcki, di, lrci) v dd = 3.2 to 5.5 v, v ss = 0 v, t a = - 20 to 80 c reset timing (rst ) v dd = 3.2 to 5.5 v, v ss = 0 v, t a = - 20 to 80 c control inputs (dsf1, dsf2) v dd = 3.2 to 5.5 v, v ss = 0 v, t a = - 20 to 80 c parameter symbol rating unit min typ max bcki high-level pulsewidth t bcwh 50 ns bcki low-level pulsewidth t bcwl 50 ns bcki pulse cycle t bcy 100 ns din setup time t ds 50 ns din hold time t dh 50 ns last bcki rising edge to lrci edge t bl 50 ns lrci edge to ?st bcki rising edge t lb 50 ns parameter symbol condition rating unit min typ max rst low-level reset pulsewidth t rst at power-on 1 s at all other times 50 ns parameter symbol condition rating unit min typ max rise time t r 10 to 90% level 100 ns fall time t f 90 to 10% level 100 ns lrci 1.5v bcki t bcy t bcwh t bcwl t ds t dh t bl t lb din 1.5v 1.5v
sm5841h nippon precision circuits? output timing standard voltage: v dd = 4.5 to 5.5 v, v ss = 0 v, t a = - 20 to 80 c, c l = 15 pf low voltage: v dd = 3.2 to 4.5 v, v ss = 0 v, t a = - 20 to 80 c, c l = 15 pf parameter symbol condition rating unit min typ max cki to cko delay t cko cki fall to cko fall 30 ns cki to bcko delay t sbh cki fall to bcko rise 10 60 ns t sbl cki fall to bcko fall 10 60 bcko to dol, dor, wcko delay t bdh bcko fall to output rise 0 20 ns t bdl bcko fall to output fall 0 20 rst to dol, dor delay t rdh rst fall to output fall 40 ns t rdl rst rise to output rise 40 parameter symbol condition rating unit min typ max cki to cko delay t cko cki fall to cko fall 45 ns cki to bcko delay t sbh cki fall to bcko rise 10 100 ns t sbl cki fall to bcko fall 10 100 bcko to dol, dor, wcko delay t bdh bcko fall to output rise 0 30 ns t bdl bcko fall to output fall 0 30 rst to dol, dor delay t rdh rst fall to output fall 60 ns t rdl rst rise to output rise 60 t bdl t bdh tsys cki (cksl = l) bcko dol dor wcko 0.5v dd 1.5v 1.5v t sbh t sbl cki (cksl = h) 1.5v
sm5841h nippon precision circuits? filter characteristics 8-times interpolation ?ter 8fs ?ter response with deemphasis off 8fs ?ter passband response with deemphasis off 8fs ?ter band transition response with deemphasis off parameter frequency rating (db) f @ fs = 44.1 khz min typ max passband attenuation 0 to 0.4535fs 0 to 20 khz 0.20 passband r ipple - 0.03 +0.03 stopband attenuation 0.5465fs to 3.4535fs 24.1 to 152 khz 53 3.4535fs to 4.5465fs 152 to 201 khz 50 4.5465fs to 7.4535fs 201 to 328 khz 53 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 frequency (fs) attenuation (db) 0.000 0.125 0.250 0.375 0.500 0.0001 0.00005 0.00000 -0.00005 -0.0001 frequency (fs) attenuation (db) 70 60 50 40 30 20 10 0 0.440 0.465 0.490 0.515 0.540 0.565 0.590 0.615 0.640 frequency (fs) attenuation (db)
sm5841h nippon precision circuits?0 deemphasis ?ter passband response with deemphasis on (fs = 44.1 khz) passband response with deemphasis on (fs = 32/48 khz) parameter sampling frequency 32 khz 44.1 khz 48 khz passband bandwidth (khz) 0 to 14.5 0 to 20.0 0 to 21.7 deviation from ideal character istic 1 attenuation (db) - 0.40 to +0.40 - 0.05 to +0.15 - 0.30 to +0.05 phase, q ( ) - 2 to 19 - 1 to 15 - 1 to 14 1. the maximum d eviation from an ideal ?ter with 0 db attenuation and 0 phase character istics for a 1 khz input signal. attenuation (db) 0 2 4 6 8 10 frequency (hz) 10 20 50 100 200 500 1k 2k 5k 10k 20k attenuation (db) 0 2 4 6 8 10 frequency (hz) 10 20 50 100 200 500 1k 2k 5k 10k 20k 32khz 48khz
sm5841h nippon precision circuits?1 functional description the basic arithmetic block is shown in ?ure 1, and the function of each block is described in the follow- ing sections. 8-times oversampling (interpolation) the interpolation arithmetic block is comprised of 3 cascaded, 2-times fir interpolation ?ters, as shown in ?ure 1. the input signal is sampled at rate fs, and then 8- times oversampling data is output. sampling noise in the 0.5465fs to 7.4535fs stopband is removed by the interpolation ?ter. digital deemphasis (dsf1, dsf2) the digital deemphasis ?ter has the same construc- tion as analog ?ters. it is implemented as an iir ?- ter to faithfully reproduce the gain and phase characteristics of standard analog deemphasis ?ters. the ?ter coef?ients for fs = 32.0/44.1/48.0 khz sampling frequency are selected by dsf1 and dsf2 when the sampling frequency is speci?d, as shown in the following table. figure 1. arithmetic block diagram input fs 13th - order 2 interpolator 2fs 4fs 69th - order 2 interpolator 8fs fs fs fs 9th - order 2 interpolator attenuator deemphasis iir filter 1st fir 3rd fir 2nd fir output dsf1 dsf2 deemphasis sampling frequency low low on 44.1 khz low high on 48.0 khz high low off high high on 32.0 khz
sm5841h nippon precision circuits?2 system clock (cki, cko, cksl ) two system clock frequencies, 384fs and 256fs, can be used. the clock is input on cki. the cki input inverter has a feedback resistor to allow ac-coupled input clocks. the system clock is also buffered and then output on cko. the system clock frequency selection and the internal clock frequency are shown in the following table. noise shaper and i/o data length (wsl1, wsl2) the sm5841h has functions that can be used to sup- press the level of requantization noise due to the inherent arithmetic rounding-off that occurs in digi- tal signal processing. n 16/18-bit input the input interface accepts 16 and 18-bit input source data. that means that if 16-bit source data is digitally processed, for example in a sound ?ld control or other dsp, the output can be input to the sm5841h without the same need for rounding- off, thereby avoiding the requantization noise that would otherwise occur. n 16/18/20-bit output the output interface can support 18 and 20-bit output data, making connection to 18 or 20-bit d/a converters possible. as a result, the requanti- zation noise generated after digital processing can be greatly reduced. n noise shaper function the 1st-order noise shaper processing occurs on the digital ?ter output. it reduces the requantiza- tion noise for 16 and 18-bit input signals to levels inherent in 18 and 20-bit output modes, respec- tively. the noise shaper does no processing on 20- bit output data. there are 4 input data and output data length combi- nations possible, selected by the state of wsl1 and wsl2 as shown in the following table. parameter cksl high low cki input system clock frequency (f sys ) 384fs 256fs cko clock frequency 384fs 256fs internal clock frequency 128fs 128fs serial output clock frequency 192fs 256fs figure 2. clock generator circuit cksl cki cko 1 / 3 internal system clock (128fs) to timing controller 1 / 2 to timing controller cksl = h cksl = l wsl1 wsl2 noise shaper input bit length output bit length high high off 18 bits 20 bits high low on 18 bits 18 bits low high on 16 bits 18 bits low low on 16 bits 16 bits
sm5841h nippon precision circuits?3 audio data input (din, bcki, lrci) the input data is in 16/18-bit serial, 2s complement, msb ?st format. serial input data on din is clocked into an sipo (serial in, parallel out) register on the rising edge of the bcki bit clock, and then converted to parallel data. sipo output data is transferred into the left and right-channel input registers on the falling edge and rising edge, respectively, of the lrci clock. the internal arithmetic operation and output circuit timing is independent of the input timing. accord- ingly, phase differences between lrci, bcki and cki do not affect device operation, and any jitter in the data input clock does not cause jitter in the output clock. note that the device should be reset if either or both of the lrci and cki clocks stop. if the device is not reset, even though the clocks are low frequency, incorrect circuit operation may occur, generating unwanted output noise. figure 3. audio data input timing din lrci bcki msb lsb 1/fs lch 16 / 18bit 16 / 18bit msb lsb rch
sm5841h nippon precision circuits?4 audio data output (dol, dor, bcko, wcko, ofst) the output data is in 16/18/20-bit serial, 8fs, simulta- neous left and right-channel, 2s complement, msb ?st format. a dc offset can be added to arithmetic data before the data is output to reduce the d/a converter zero- crossing distortion for very small input signals. the offset added is approximately 0.8% of full-scale for the corresponding output bit length, as shown below. n 512 lsb for 16-bit output n 2048 lsb for 18-bit output n 8192 lsb for 20-bit output the dc offset is added to the output when ofst is high. dc offset is off when ofst is low. 8fs serial data is output on independent dol and dor channels, in sync with the falling edge of the internal system clock and bcko clock. the number of bcko bit clock pulses per word changes depend- ing on the output bit length selected (16/18/20 bits). consequently, output data is latched into the d/a converter internal register on the falling of the edge of an output word clock wcko, which has timing independent of the number of output bits as speci?d in the following table. parameter symbol cksl = high cksl = low bit clock rate t b t sys (1/192fs) t sys (1/256fs) data w ord length t dw 24t b 32t b the n umber of output bits is deter mined by the output bit length selected. figure 4. 8fs data output timing (cksl = high) the n umber of output bits is deter mined by the output bit length selected. figure 5. 8fs data output timing (cksl = low) 12 4 35 11 12 14 13 15 16 17 19 18 20 12 4 3 6tb 18tb t dw = 24tb system clock bcko dol or dor wcko tb 12 4 35 11 12 14 13 15 16 17 19 18 20 12 4 3 6tb 26tb t dw = 32tb system clock bcko dol or dor wcko tb
sm5841h nippon precision circuits?5 system reset and output muting (rst ) system reset the sm5841h must be reset at power-on by apply- ing a low-level pulse on rst . at system reset, the arithmetic and output timing counters are reset on the next lrci start edge, as long as the cki clock has already stabilized. the power-on reset pulse can be applied by a microcontroller or, for systems where cki and lrci are stable at power-on, by connecting a 300 pf capacitor between rst and vss. for systems that do not use a microcontroller, the capacitor must be cho- sen such that the cki and lrci clocks fully stabilize before rst goes from low to high. if the system clock is interrupted or is corrupted by jitter, after power-on reset and all internal timing is synchronized, such that a timing error greater than ?/8 f lrci occurs, the internal timing is automati- cally reset on the next lrci start edge. this resyn- chronization affects the internal operation and can generate a momentary click noise output. output muting when rst goes low, the dol and dor outputs go low, immediately muting the output signal, and they remain low for intervals in word units. muting is released and timing is synchronized on the 3rd ris- ing edge of lrci after rst goes high. note that during muted output, the bcko and wcko clocks do not stop. figure 6. system reset timing and output muting lrci internal reset dol dor (l) (l) 1234 rst
sm5841h nippon precision circuits?6 timing diagrams input timing examples (din, bcki, lrci) figure 7. 18-bit input timing figure 8. 16-bit input timing bcki lrci din 18bit rch (msb) (lsb) 1 / fs 18bit lch (msb) (lsb) bcki lrci din 16bit rch (msb) (lsb) 1 / fs 16bit lch (msb) (lsb) audio ics
sm5841h nippon precision circuits?7 output timing examples (dol, dor, bcko, wcko) the n umber of output bits is deter mined by the output bit length selected. figure 9. 8fs data output timing (cksl = high) the n umber of output bits is deter mined by the output bit length selected. figure 10. 8fs data output timing (cksl = low) 12 4 35 11 12 14 13 15 16 17 19 18 20 12 4 3 6tb 18tb t dw = 24tb system clock bcko dol or dor wcko tb 12 4 35 11 12 14 13 15 16 17 19 18 20 12 4 3 6tb 26tb t dw = 32tb system clock bcko dol or dor wcko tb
sm5841h nippon precision circuits?8 application circuits input interface circuits matsushita mn6617 xck r / l srdata srck cki lrci din bcki sm5841h wsl1 sel 16.9344mhz 44.1khz 2.1168mhz sony cxd2500 c16m lrdk da16 da15 cki lrci din bcki cksl sm5841h wsl1 pssl 16.9344mhz 44.1khz 2.1168mhz cksl yamaha ym3623 oa l / r do bco cki lrci din bcki sm5841h wsl1 16.9344mhz 44.1khz 2.1168mhz cksl toshiba tc9200f 17mo chck dout bck cki lrci din bcki sm5841h wsl1 16.9344mhz 44.1khz 2.1168mhz cksl ipsel
sm5841h nippon precision circuits?9 output interface circuits 18-bit, 2-dac (8fs l+r output mode) 16-bit, 1-dac (8fs l+r output mode) this example is for 16-bit input mode, so wsl1 is tied high. for 18-bit mode, wsl1 is tied low. sm5841h (16bit input) wcko dol dor bcko clock l. e. data burr - brown pcm58p wsl1 lch output burr - brown pcm58p clock l. e. data rch output sm5841h (16bit input) wcko dol dor bcko wsl1 lch output wsl2 rch output wcko lsi rsi clk nec m pd6376 4/8fs sel
sm5841h nippon precision circuits?0 nippon precision circuits inc. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsib ility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and nippon p recision circuits inc. makes no claim or warranty that such applications will be suitable for the use speci?d without further testing o r modi?ation. the products described in this data sheet are not intended to use for the apparatus which in?ence human lives due to the failu re or malfunction of the products. customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. customers shall not export, dir ectly or indirectly, any products without ?st obtaining required licenses and approvals from appropriate government agencies. nippon precision circuits inc. 4-3, fukuzumi 2-chome koto-ku, tokyo 135-8430, japan telephone: 03-3642-6661 facsimile: 03-3642-6698 nippon precision circuits inc. nc9625ae 1998.06

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